The current damascene plating process and especially that for copper requires a copper seed as a conductive layer on top of the highly resistive barrier liner which covers the underlying substrate such as a patterned wafer. The continuous miniaturization of ULSI technology will eventually require the elimination of this copper seed layer. Without this conductive seed, an applied current or voltage will drop off drastically within a short distance from the edge where the electrical contact is made (as will be described below.) As a result of this so-called terminal effect, a sufficient overpotential, η, for copper deposition will only exist near the edge of the substrate and plating is observed at the edge of the substrate only. When applied current is based on the total area of the substrate the effective current density for the perimeter ring is much higher and as a result burned, powdery deposits are obtained.
Conventional methods to overcome the terminal effects for thin seed layers such as low plating current, segmented anode configuration, high copper concentration and low conductivity (low acid concentration) copper plating baths improve the current distribution and result in a more uniform film thickness. However, these methods apply only in the case where a sufficient plating overpotential exists over the whole substrate surface, from edge to center. For very thin seed layers and more importantly in the absence of a seed layer, the terminal effect of the resistive liner or seed causes such a drastic increase in the potential of the liner material, Um(r), from the edge (r=r0) to center (r=0) of the wafer, that the overpotential, η, becomes zero at a certain distance from the electrical contact and no further plating can occur:η=Ueq,Cu2+/Cu−Um(r)  (1)with Ueq,Cu2+/Cu the equilibrium potential (Nernst potential) for copper deposition.
Copper deposition will proceed when η>0, i.e. when Um(r)<Ueq,Cu2+/Cu, as illustrated schematically in the energy diagram for a metal/electrolyte interface shown in FIG. 1. FIG. 2a shows the variation of the plating overpotential in the case of a thin copper seed and FIG. 2b in the case of the highly resistive liner material on extremely thin copper seeds. For the 60 nanometer copper seed, the sheet resistance is still low enough to ensure deposition over the whole substrate surface, although with a non-uniform growth rate in the case of a primary current distribution. The drop-off in the overpotential is much more severe for the highly resistive liner, and becomes zero at a certain distance, x=r0−r, from the edge of the wafer. In this case deposition is only observed at the edge of the wafer. Additionally, too low current or overpotential results in a low density of nucleation sites leading to powdery, poorly adherent deposits. Although the example of copper deposition on liners is used above to facilitate an understanding of this invention, the principle of seedless plating holds for the deposition of any conductive material (metal, compound, alloy, composite, semi-metal or semiconductor) onto a resistive substrate.